Boundary scan testing is very well known in the art and is supported by an IEEE standard (IEEE 1149.1) which details its implementation and operation modes. FIG. 1 illustrates the logic arrangement of a prior art boundary scan cell for use in boundary scan testing at IC outputs. The boundary scan cell contains an input multiplexer (Mux1), a capture/shift memory (Mem1) such as a flip-flop or other latch circuit, an output memory (Mem2) such as a flip-flop or other latch circuit, and an output multiplexer (Mux2). Mux1 is controlled by a select signal (Select 1) to allow Mem1 to load data from either the serial data input or the system data output by the IC core logic. Mem1 loads data in response to a control signal (Control 1). The output of Mem1 is input to Mem2 and is output as serial data. Mem2 loads data from Mem1 in response to a control signal (Control 2). Mux2 is controlled by a select input (Select 2) to allow it to output to the IC's output buffer either the output of Mem2 or the system data from the IC core logic. A plurality of these boundary scan cells can be connected serially, via the serial input and output lines, to form a boundary scan register.
In FIG. 1, the output boundary scan cell logic is enclosed in dotted lines. The boundary scan cell connects an output from the IC's core logic to the IC's output buffer. The output buffer outputs a high (V+) or low (G) voltage in response to the logic level it receives from Mux2. The boundary scan cell is realized in the same region of the IC as the core logic, i.e., the core region. In most instances, i.e. when implemented in accordance with the rules stated in the IEEE 1149.1 standard, the boundary scan cell logic is dedicated for test purposes and is not shared with system logic functions. In this way, the boundary scan cell can be accessed for non-intrusive test operations without disturbing the IC's normal functional operation.
The IEEE 1149.1 standard defines three types of test operations for boundary scan cells, a sample test operation (Sample), an external test (Extest) and internal test (Intest). Sample is a required test mode for 1149.1. During Sample, the IC is in normal operation (i.e. IC's core logic is connected to the output buffers via Mux2) and Mux1 and Mem1 are operated to capture and shift out normal IC output data. Extest is another required test mode for 1149.1. During Extest, output boundary scan cells are used to drive test data from IC outputs onto wiring interconnects, and input boundary scan cells are used to capture the driven test data at IC inputs. In this way, Extest can be used to test wiring interconnects between IC inputs and outputs on a board. Intest is an optional test mode for 1149.1. During Intest, input boundary scan cells are used to drive test data to the IC's core logic, and output boundary scan cells are used to capture the response from the core logic. In this way, Intest can be used to test IC core logic.
During normal IC operation, the output of the IC's core logic passes through Mux2, to the output buffer, and is driven off the IC by the output buffer. Therefore, during normal mode, the IC output function is not effected by the boundary scan cell, except for the delay introduced by Mux2. If, during normal operation, a Sample is performed, the boundary scan cell receives Select 1 and Control 1 input to capture system data and shift it out for inspection via the serial output.
During test operation, the output of the ICs core logic is received by the boundary scan cell for capturing and shifting, but Mux2 is controlled by Select 2 to output the test data stored in Mem2 to the output buffer. Therefore, during test mode, the IC core logic output function is disabled by the boundary scan cell. If, during test operation, an Extest or Intest is performed, the boundary scan cell receives Select 1 and Control 1 inputs to capture system data into Mem1 and shift it out for inspection via the serial output. While Mem1 is capturing and shifting data, Mem2 outputs stable test data to the output pin. After Mem1 has completed its capture and shift operation in Extest it contains new test data to be loaded into Mem2. Mem2 loads the new test data from Mem1 in response to a signal on Control 2. After Mem2 receives the new test data, it is output from the IC via Mux2 and the output buffer. The purpose for Mem2 is to latch the IC's output at a desired test logic state while Mem1 is capturing and shifting data. Without Mem2, i.e. if the output of Mem1 were connected to Mux2 directly, the IC's output would transition between logic (i.e. ripple) states as data is captured into and shifted through Mem1.
Examples of the boundary scan cell of FIG. 1 performing Sample, Extest and Intest operations are illustrated in the timing diagram of FIG. 1A. In the timing diagram of FIG. 1A and all following tiling diagrams, "C" indications on the Control 1 and Control 2 signals indicate a low-high-low signal sequence which, in the example circuits shown, provides the control to store data into Mem1 and Mem2, respectively. Logic zero and one levels on the Select 1 and Select 2 signals indicate logic levels used to control the operation of Mux1 and Mux2, respectively. Also, seven Control 1 "C" signals are used in all example timing diagrams. The first Control 1 "C" signal indicates the capture of data into Mem1, and the following six Control "C" signals represent the shifting of data through six serially connected boundary scan cell circuits.
In FIG. 2, a known improvement to the boundary scan cell of FIG. 1 is shown. The improvement is brought about by realizing Mux2 in the buffer region of the IC's output buffer. Relocating test logic in the IC buffer region frees up area in the IC's core logic for system (non-test) logic functions. The logic required in the IC's core region is reduced by the size of Mux2 for each required output boundary scan cell. This leaves only the boundary scan cell's Mux1, Mem1, and Mem2 as test logic overhead in the IC's core region. The amount of boundary scan cell logic that needs to be placed and routed in the IC's core region is reduced. The boundary scan cell of FIG. 2 operates exactly like the one of FIG. 1.
FIG. 3 illustrates another known improvement to the boundary scan cell of FIG. 1. This improvement was described in 1990 by D. Bhavsar on pages 183-189 of IEEE Society Press Publication "Cell Designs that Help Test Interconnection Shorts". The improvement allows the logic output from the output buffer to be captured and shifted out of Mem1 during Extest. This feature allows detecting shorts between pins or to supply voltages or ground that conflict with the logic level attempting to be driven out of the output buffer. For example, during Extest, if a logic one is driven from Mem2 the output buffer will attempt to drive out a logic one. However, if the output of the output buffer is shorted to ground a high current (or low impedance) path exists in the output buffer from V+ through the top transistor to ground, which can result in a damaged or destroyed output buffer. Similarly if Mem2 is driving out a logic zero and the output of the output buffer is shorted to a supply voltage, a high current (low impedance) path exists through the bottom transistor to ground (G), again resulting in a damaged or destroyed output buffer. The boundary scan cell of FIG. 3 allows detecting these short circuit conditions by the addition of a third multiplexer (Mux3), a third select input (Select 3), and an input buffer. The input buffer inputs the logic state at the output of the output buffer. Mux3 inputs the system data and the logic state of the output buffer, via the input buffer, and outputs a selected one of these signals to one input of Mux1. In this example, Mux3 selects the system logic if Select 3 is low (Intest) or the output buffer state if Select 3 is high (Extest). In this way, Mem1 captures and shifts system data from the IC's core logic during Sample and Intest, and test data from the input buffer during Extest.
Examples of the boundary scan cell of FIG. 3 in Sample, Extest, and Intest operation are illustrated in the timing diagram of FIG. 3A. The boundary scan cell of FIG. 3 also allows reducing the time that an output can be shorted. In the timing diagram of FIG. 3B, it is seen that after a full Extest operation, Extest 1 (i.e. the Capture & Shift of Mem1 and the Updating of Mem2), a short Extest operation, Extest 2 (i.e. the Capture Only of Mem1 (no shift) and Update of the captured data to Mem2), can be performed. The Extest 2 operation allows test data from the output to be updated into Mem2 to correct any voltage conflict on the output. For example, if the Extest 1 operation had attempted to output a logic one on the output buffer, with the IC output shorted to ground, and the Extest 2 operation captured and updated a logic zero (due to the short to ground), the amount of time the output buffer was in the high current situation (V+ to G through top transistor) is reduced to the number of TCK periods it takes to go from the update step of Extest 1 to the update step of Extest 2, TCK being, for example, the test clock of IEEE 1149.1. The next full Extest operation (Extest 3) captures and shifts out the logic zero to indicate the short to ground and the resulting change in state of Mem2, brought about by the short Extest operation (Extest 2). If no short to ground existed, then the Extest 2 operation would have reloaded Mem2 with the logic one from the Extest 1 operation, and the Extest 3 operation would have verified the logic one at the IC output.
While this approach reduces the amount of time a voltage conflict can exist at an IC output, the time it takes to execute the corrective Extest scan operations, i.e. Extest 1 to Extest 2 update times in FIG. 3B, may still endanger the output buffer. Also when the IC is first powered up in its normal mode, output conflicts due to shorts can exist for an extended amount of time before a test mode is entered, if entered at all. So while the boundary scan cell of FIG. 3 does provide short circuit detection and correction improvements over the one in FIG. 1, it requires time to make the corrections and does not provide protection at power up where the IC immediately enters its normal operation. Also the boundary scan cell of FIG. 3 requires an additional Mux3, Select 3 signal, and input buffer to achieve the short circuit detection and correction feature.
It is desirable in view of the foregoing to implement at least the functionality of the prior art boundary scan cells using less of the IC core area. To this end, the present invention: provides a boundary scan cell that requires less logic in the IC core region than prior art boundary scan cells; utilizes the IC output buffer as part of output boundary scan cells, and the IC input buffer as part of input boundary scan cells; provides latchable input and output buffer circuits that serve the function of Mem2 in the prior art boundary scan cells; integrates the functions of Mux2 and Mem2 into IC input and output buffers to facilitate boundary scan cell logic reduction in the IC core region; provides a boundary scan cell and output buffer combination that can immediately and asynchronously detect and correct short circuit conditions on output pins during Extest operation; provides a boundary scan cell and output buffer combination that can immediately and asynchronously detect and correct short circuit conditions on output pins when the IC is initially powered up in its normal mode; and provides an IC power up method and procedure that prevents IC output buffers from being damaged or destroyed by short circuits.